Job title : Layout Engineer
Job Number :
Division : Engineering
• Custom layout of analogue circuits at the block and chip level in low and high voltage CMOS technologies.
• Completion of layout through DRC, ERC, LVS and Extraction flows using a combination of leading edge and customised CAD tools.
• Adherence to best practice for current carrying, parasitic minimisation and compactness.
• Teamwork with circuit designers to optimise and sign off work.
Minimum Experience Requirements:
• Of emphasis is first-hand experience of CMOS integrated circuit layout in a commercial and results driven environment.
• Proficiency with leading CAD layout tools and flows (Cadence, Mentor) and UNIX scripting environments.
• Good time management and communications skills for efficient and effective results, and the ability to participate as a team member.
• Good communications skills in English to a level that you are able to confidently present designs to colleagues at design reviews.
• Good knowledge of device physics is a strong plus
Requirements: BSEE and 3 years of industry experience.